1. Field of the Invention
The present invention relates generally to data transmission networks, and more particularly, to methods and systems for latching received data for subsequent use.
2. Description of the Related Art
A jam latch is a circuit that is typically used to capture data being output from a previous circuit or device in a data system. The jam latch temporarily holds the data so that a subsequent device or circuit can read the data. In this manner the data can be accurately captured so that the subsequent stage can use the correct data level. The jam latch circuit can also increase the power of (i.e., amplify) the data signal. By way of example a jam latch can be used to capture data on a data bus for a device coupled to the data bus, amplify the captured data and then output the captured data to the coupled device.
FIG. 1 is an exemplary prior art jam latch circuit 100. A cross-coupled latching inverter pair X1, X2 latches high whenever either of the DATA IN 1 or DATA IN 2 signals go low. By way of example, when DATA IN 1 switches to a low state voltage, transistor M3 begins to conduct which applies a high state voltage to DD_SIN. DD_SIN in the high state causes the inverter pair X1, X2 to latch in a high state and maintain a high signal level applied to DD_SIN even after M3 stops applying the high state voltage to the DATA IN 1 (i.e., when M3 stops conducting). Similarly, when DATA IN 2 goes low, transistor M0 conducts a high state to DD_SIN, which can also cause inverter pair X1, X2 to latch in a high state.
When DD_SIN is high, inverter X0 inverts DD_SIN to output a low state SIN_1 signal. The SIN_1 signal is applied to input 102A of nand gate X3. As long as at least one of inputs 102A, 102B, 102C is low on nand gate X3, then DD_OUT will be a high state. The low SIN_1 is output from inverter X0 a time delay referred to as a “one gate delay” from when the DD_SIN goes high. The one gate delay is caused by the time required for the inverter X0 to switch from one state to the other (i.e., from high state to low state).
The inverter pair X1, X2 remains latched high (and therefore DATA OUT high) until all of the reset transistors M1, M5, M7 conduct at the same time. When all the reset transistors M1, M5, M7 conduct, a low signal level (i.e. ground potential) is applied to the inverter pair X1, X2 (i.e., the high state voltage of the inverter pair is pulled down to a low potential). Thus the inverter pair X1, X2 is reset to a low state. As shown, reset transistor M5 will conduct when DATA IN 1 is high, reset transistor M1 will conduct when DATA IN 2 is high, and reset transistor M7 will conduct when the clock signal (CLK) goes high. One or more additional reset transistors (not shown) can also be included in series with the reset transistors M1, M5, M7 such as to allow an additional reset condition control (e.g., an enable control). Resetting the inverter pair X1, X2 is a “three gate delay” as the resulting data output will not change until the inverter pair X1, X2, the inverter X0 and the nand gate X3 switch states.
When the inverter pair X1, X2 is reset to a low state, a low state is applied to the DD_SIN. The inverter X0 inverts the low DD_SIN to output a high SIN_1. A high applied to each of the nand gate X3 inputs 102A, 102B, 102C causes the DATA OUT to be low.
Both the input and the output of keeper circuit K1 are coupled to DATA IN 1. Keeper circuit K1 includes an inverter XK1 that has an input coupled to the DATA IN 1 and an output coupled to the base terminal of a transistor MK1. The transistor MK1 has an input coupled to a high state potential and an output coupled to the DATA IN 1. When the DATA IN 1 goes high, the XK1 outputs a low potential that will enable transistor MK1 thereby causing transistor MK1 to conduct the high state potential to DATA IN 1. Keeper circuits K1, K2 support the dynamic logic level on the respective data lines DATA IN 1 and DATA IN 2, so that the logic level does not leak down (or up) to an incorrect or ambiguous logic level.
As described above, the jam latch 100 captures when the data level goes low on either of the DATA IN 1 and DATA IN 2 data lines and, one gate delay later, outputs a high signal level from the nand gate X3. The jam latch 100 can also amplify the data signal level so that the signal levels on DATA IN 1 and DATA IN 2 can be very low (e.g., 0.0 v=low state and 0.3 v=high state) and DATA OUT have much higher signal voltages (e.g., 1.0 v=low state and 5.0 v=high state) and power levels so that subsequent devices can be driven by the DATA OUT output voltage and current.
The prior art jam latch circuit 100 has several shortfalls that limit, for example the scalability of the jam latch circuit. The short falls include excessive internal loads and excessive switch time (i.e., switch speed too slow). The excessive internal loads require larger circuit elements (i.e., device size) therefore uses more power and geography on the semiconductor die. By way of example, DATA IN 1 is connected to three devices: keeper K1 and transistors M3 and M5. Each of the three devices K1, M3 and M5 form a parasitic load on the DATA IN 1 data line. As a result, this parasitic load can increase the switching time of the DATA IN 1 data line as these parasitic loads must also be charged or discharged as the state of the DATA IN 1 data line changes. This parasitic load can be a greater proportion of the total load as the gain of the jam latch 100 is reduced. By way of example, in a jam latch having a gain of 16 (i.e., 16 times power amplification), the total load is substantially greater than in a similar jam latch having a gain of 4, while the parasitic load caused by keeper K1 and transistors M3 and M5 remain constant in either of the jam latches.
Further, each of the series reset transistors M1, M5 and M7 are sized the same so that they switch substantially identically. The series reset transistors M1, M5 and M7 must also be sized to sink the current conducted across the series reset transistors. In the typical two data line jam latch 100, series reset transistors M1, M5 and M7 have a device size of 5.76 micron. In a similarly designed three data line jam latch, the corresponding series rest transistors M1, M5 and M7 and an additional transistor (i.e., for the third data line) would have a device size of 7.2 micron so as to be able to handle the increased current demands caused by the additional series transistor. In yet another similarly designed four data line jam latch circuit, the series reset transistors would be even larger. As a result, the design of the jam latch 100 cannot be efficiently scaled to include more than two or possibly three data lines. As the device sizes of the series rest transistors M1 and M5 increases their corresponding parasitic loads of the corresponding data lines (i.e., DATA IN 2, DATA IN 1, respectively) are also increased, further degrading the switching performance of the data lines.
In addition, as the device size of the series reset transistors increase, the space required for the larger devices increase and can therefore consume excessive area of the semiconductor die. Further, the increased current load of the larger device sizes increases the overall current load and the resulting heat dissipation required for the jam latch circuit. The increased heat load can further complicate the design and placement of the jam latch components. Larger devices typically also have slower switching times at the same current level or require additional current to cause the switching time to remain approximately comparable to a similar smaller device. In view of the foregoing, there is a need for a scalable, power efficient jam latch circuit.